The designing of a semiconductor integrated circuit device (LSI) includes timing verification to verify and ensure the operation of a logic circuit. In the timing verification, information on the wiring length, wiring width, and wiring interval is extracted from pattern data of an LSI, the layout of which has been designed. Then, a timing analysis is conducted on the LSI circuit taking into consideration the delay time and characteristics of the LSI circuit that are caused by the wiring resistance and the wiring capacitance (refer to Japanese Laid-Open Patent Publication Nos. 2001-306647, 2004-362202, and 2006-278613). Based on the timing analysis results, the appropriateness of the LSI circuit is determined and corrections are made to the circuit when necessary.